1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device.
2. Description of the Related Art
As a representative of nonvolatile semiconductor storage devices, there is flash memory. Data readout of a nonvolatile semiconductor storage device is performed by comparing a memory cell current of a memory cell that becomes a readout target with a reference current, and determining the logic level of the data that have been read out. For example, in a binary memory cell, when the memory cell current is smaller than the reference current, the logic level becomes “0”. On the other hand, when the memory cell current is larger than the reference current, the logic level becomes “1”.
A memory cell current of logic levels “0” and “1” is distributed having variation to a certain extent, because of variation in the characteristics of the memory cell. Consequently, a conventional nonvolatile semiconductor storage device sets the reference current near, for example, the center of a region (hereinafter called a current window) with which the distribution of the memory cell current of logic levels “0” and “1” does not overlap and determines the logic level.
FIG. 26A shows a distribution of a memory cell current of logic levels, a current window, and a reference current set in the center of the current window.
Conventionally, this reference current is generated using a reference memory cell or a constant current source. When the reference memory cell is used, the average value of the memory cell current of logic levels can be used as the reference current. Further, the average value of a memory cell current adjusted to a reference current at the time of writing, and a memory cell current adjusted to a reference current at the time of erasure can be used as the reference current.
When a constant current source is used as the method of generating the reference current, a constant current source adjusted near, for example, the center of the current window can be used.
In Japanese Patent Application Laid-Open (JP-A) No. 2006-134536, there is disclosed a readout circuit that compares the reference current with a memory cell current. This circuit combines or appropriately selects a memory cell current set to a minimum value of the memory cell current after erasure, and a memory cell current set to a maximum value of the memory cell current after writing.
In recent years, current windows are becoming smaller because of miniaturization and value multiplexing of memory cells. For this reason, the importance of reference current characteristics and precision is growing.
When the reference memory cell is used to generate the reference current, like a normal memory cell that becomes a readout target, the memory cell current is adjusted by writing control. Consequently, characteristic fluctuation of the reference memory cell resulting from use conditions, such as a bias voltage and temperature, matches with a normal memory cell. However, the reference current also ends up varying just as a normal memory cell current varies.
FIG. 27A shows how the reference current varies, when the reference memory cell is used. Further, FIG. 27B shows how the reference current moves as the distribution of the memory cell current of logic levels “0” and “1” moves because of characteristic fluctuation.
On the other hand, when a constant current source is used for the reference current, the current value can be adjusted with high precision. However, in this case, characteristic fluctuation resulting from use conditions, such as a bias voltage and temperature, does not match with a memory cell. For this reason, the reference current ends up being away from the center of the current window because of use conditions, and the readout margin ends up worsening.
FIG. 28A shows how the reference current can be set with high precision, when a constant current source is used. Further, FIG. 28B shows how, as the distribution of a memory cell current of logic levels “0” and “1” moves because of characteristic fluctuation, movement resulting from characteristic fluctuation of a reference current does not match, and the readout margin worsens. FIG. 28B shows how the readout margin of logic level “0” worsens. When characteristic fluctuation is in the opposite direction, the readout margin of logic level “1” worsens.
As mentioned above, the circuit described in JP-A No. 2006-134536 combines or appropriately selects a memory cell current set to a minimum value of the memory cell current after erasure, and a memory cell current set to a maximum value of the memory cell current after writing. However, this circuit cannot move the reference current with high precision to the center of the current window, in response to characteristic fluctuation of the memory cell.